Altera ArriaGX FPGA入门开发方案
发布日期：2014-01-14
Altera公司的Arria GX FPGA是带有收发器的中端FPGA系列。其收发器速率高达3.125 Gbps，您可以利用它来连接支持PCI Express,千兆以太网,Serial RapidIO,SDI等协议的现有模块和器件。具有同类最佳的信号完整性, 是功耗最低的中端FPGA，适用于需要32个支持背板的6.5536 Gbps收发器的应用.本文介绍了Arria®GX FPGA主要特性和架构图,以及Arria V GX FPGA入门开发板主要特性,框图,电路图,PCB元件布局图和材料清单.
Arria®GX FPGA是Altera带有收发器的中端FPGA系列。其收发器速率高达3.125 Gbps，您可以利用它来连接支持PCI Express、千兆以太网、Serial RapidIO、SDI等协议的现有模块和器件。Arria GX FPGA含有Altera的第四代收发器，确保您的设计具有优异的信号完整性。
同类最佳的信号完整性
Arria GX收发器基于最初为Stratix II GX FPGA系列开发而大获成功的技术之上。所有系列均采用90nm工艺技术生产，使用相同的物理介质附加(PMA)电路。Arria GX还含有Stratix II GX FPGA物理编码子层(PCS)的子集。结合倒装焊封装，这些特性在低成本收发器FPGA中实现了同类最佳的信号完整性。
获得大奖的软件工具和IP，提高了效能
Altera的Quartus II 和SOPCBuilder帮助您迅速轻松地将设计构思实现为最终产品。Quartus II 以最快的编译时间和精确的结果帮助您提高效能。利用SOPCBuilder，您可以在简单直观的图形界面下，无缝连接知识产权(IP)模块。此外，Timequest是强大的ASIC功能时序分析器，支持业界标准Synopsys设计约束(SDC)格式。
世界范围内的高速专家网络
当器件需要连接高速接口时，您可以咨询Altera的系统级专家们，通过MySupport在线接触专家，或者联系当地的现场应用工程师组。每一地区支持中心(RSC)的高速串行接口系统专家在MySupport上回答您提出的问题。Altera在北美设立了RSC应用工程师组。
The Arria® V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-range FPGA bandwidth 12.5 Gbps transceivers.
The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (DSP) applications.
Arria®GX FPGA主要特性:
■ Transceiver block features
■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.
■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels
■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode
■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers
■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)
■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices
■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO
■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
■ Channel aligner compliant with XAUI
■ Main device features:
■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz
■ Up to 16 global clock networks with up to 32 regional clock networks per device
■ High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting
■ Support for numerous single-ended and differential I/O standards
■ High-speed source-synchronous differential I/O support on up to 47 channels
■ Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■ Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)
■ Support for remote configuration updates
图1. Arria V FPGA体系结构框图
Arria V GX入门开发板
The Arria V GX starter board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GX designs.
One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera® and various partners.
Arria V GX入门开发板主要特性:
■ One Arria V GX 5AGXFB3H4F35C4N FPGA in a 1152-pin FineLine BGA (FBGA) package
■ 362,000 LEs
■ 136,880 adaptive logic modules (ALMs)
■ 17,260 Kbit on-die block memory
■ 24 high-speed transceivers
■ 12 fractional phase locked loops (PLLs)
■ 2,090 18x19 multipliers
■ 544 general purpose input/output
■ 1.1-V core voltage
■ MAX® V 5M2210ZF256C4N CPLD in a 256-pin FBGA package
■ MAX II EPM570F100C5N CPLD in a 100-pin FBGA package
■ FPGA configuration circuitry
■ MAX V CPLD 5M2210ZF256C4N System Controller and flash fast passive parallel (FPP) configuration
■ On-board USB-BlasterTM II for use with the Quartus® II Programmer
■ Clocking circuitry
■ Programmable clock generator for FPGA reference clock input
■ 125-MHz LVDS oscillator for FPGA reference clock input
■ 148.5/148.35-MHz LVDS VCXO for FPGA reference clock input
■ 50-MHz single-ended oscillator for FPGA and CPLD clock input
■ 100-MHz single-ended oscillator for CPLD configuration clock input
■ SMA input (LVPECL)
■ Memory
■ Two 128-Mbyte (MB) DDR3 SDRAM with a total of 32-bit data bus
■ 2-MB SSRAM
■ Two 128-MB synchronous flash
■ General user I/O
■ LEDs and displays
■ Four user LEDs
■ One two-line character LCD display
■ Three configuration select LED
■ One configuration done LED
■ Four on-board USB-Blaster II status LEDs
■ Two HSMC interface transmit/receive LED (TX/RX)
■ Four PCI Express LEDs
■ Five Ethernet LEDs
■ One serial digital interface (SDI) carrier detect LED
■ Push buttons
■ One CPU reset push button
■ One configuration reset push button
■ Three general user push buttons
■ DIP switches
■ Four MAX V CPLD System Controller control switches
■ Three JTAG chain control switches
■ Three PCI Express link width switches
■ Four general user switches
■ Power supply
■ 19-V (laptop) DC input
■ PCI Express edge connector power
■ Mechanical
■ PCI card standard size (6.600" x 4.199")
图2.Arria V GX入门开发板框图
图3.Arria V GX入门开发板外形图
Arria V GX入门开发板包括:
硬件:
• Arria V GX FPGA Starter Board running on Arria V GX 5AGXFB3H4F35C4N FPGA
• DDR3 memory
• One HSMC connector supporting LVDS and single-ended I/Os
• PCIe x8 edge connector
• High-definition multimedia interface (HDMI) output and serial digital interface (SDI) channel
• Character LCD
• Debug and loopback HSMC boards
• AC adapter power cables
• Ethernet, SMB-SMB, and USB cables
软件:
• Design examples
- Board Update Portal design
- Board Test System (BTS) design
• Documentation
- Arria V GX Starter Kit User Guide
- Arria V GX Starter Board Reference Manual
- Board design files
• Design software*
- Quartus II software (required)
- Nios® II processor (optional)
- MegaCore® intellectual property (IP) library (optional)
- Mentor Graphics® ModelSim®-Altera software (optional)
图3.Arria V GX入门开发板系统框图
图4.Arria V GX入门开发板电源树图
图5.Arria V GX入门开发板时钟树图
图6.Arria V GX入门开发板系统电路图(1)
图7.Arria V GX入门开发板系统电路图(2)
图8.Arria V GX入门开发板系统电路图(3)
图9.Arria V GX入门开发板系统电路图(4)
图10.Arria V GX入门开发板系统电路图(5)
图11.Arria V GX入门开发板系统电路图(6)
图12.Arria V GX入门开发板系统电路图(7)
图13.Arria V GX入门开发板系统电路图(8)
图14.Arria V GX入门开发板系统电路图(9)
图15.Arria V GX入门开发板系统电路图(10)
图16.Arria V GX入门开发板系统电路图(11)
图17.Arria V GX入门开发板系统电路图(12)
图18.Arria V GX入门开发板系统电路图(13)
图19.Arria V GX入门开发板系统电路图(14)
图20.Arria V GX入门开发板系统电路图(15)
图21.Arria V GX入门开发板系统电路图(16)
图22.Arria V GX入门开发板系统电路图(17)
图23.Arria V GX入门开发板系统电路图(18)
图24.Arria V GX入门开发板系统电路图(19)
图25.Arria V GX入门开发板系统电路图(20)
图26.Arria V GX入门开发板系统电路图(21)
图27.Arria V GX入门开发板系统电路图(22)
图28.Arria V GX入门开发板系统电路图(23)
图29.Arria V GX入门开发板系统电路图(24)
图30.Arria V GX入门开发板系统电路图(25)
图31.Arria V GX入门开发板系统电路图(26)
图32.Arria V GX入门开发板系统电路图(27)
图33.Arria V GX入门开发板系统电路图(28)
图34.Arria V GX入门开发板系统电路图(29)
图35.Arria V GX入门开发板系统电路图(30)
图36.Arria V GX入门开发PCB元件布局图(顶层)
图37.Arria V GX入门开发PCB元件布局图(底层)